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CSCE 611 Fall 2025 Lecture 6: RISC-V Microarchitecture: RIU Instructions

YouTubeJason Bakos

CSCE 611 Fall 2025 Lecture 6: RISC-V Microarchitecture: RIU Instructions

Topics: (1) SystemVerilog memory: latches, flip-flops, and RAM (2) The RISC-V pipeline (3) RISC-V register file (4) RISC-V ALU (5) Instruction memory / fetch stage (6) Execute and write back stage (7) Lab 3: RISC-V RIU instructions and test programs

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